IC AS7C3256A datasheet and PDF info

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< Analog Electronic ~ IC AS7C3256A datasheet and PDF info

wisdomchina

Posted: Sat May 10, 2008 3:54 pm Post subject: IC AS7C3256A datasheet and PDF info

Joined: 22 Apr 2008 Posts: 26

AS7C3256A Functional description
The IC integrated circuit AS7C3256A is a 3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins.The device enters standby mode when CE is high. CMOS standby mode consumes 7.2 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.
Equ al address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns
are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank
memory organizations.

A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7
is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.

AS7C3256A-15TCN datasheet and PDF download from ChinaICMart .

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