 | Author | Message | | | Lily-Lee | | Posted: Sun Jun 29, 2008 3:37 pm Post subject: SA568AD Description | | | | Joined: 22 May 2008 Posts: 32 | FUNCTIONAL DESCRIPTION:[url]http://www.chinaicmar t.com/series-SA5/SA568 AD.html[/url]
The NE568A is a high-performance phase-locked loop (PLL). The circuit consists of conventional PLL elements, with special circuitry for linearized demodulated output, and high-frequency performance. The process used has NPN transistors with f > 6GHz. The high T gain and bandwidth of these transistors make careful attention to layout and bypass critical for optimum performance. The performance of the PLL cannot be evaluated independent of the ayout. The use of the application layout in this data sheet and surface-mount capacitors are highly recommended as a starting point. The input to the PLL is through a limiting amplifier with a gain of 200 The input of this amplifier is differential (Pins 10 and 11). For single-ended applications, the input must be coupled through a DC-blocking capacitor with low impedance at the frequency of nterest. The single-ended input is normally applied to Pin 11 with Pin 10 AC-bypassed with a low-impedance capacitor. The input impedance is characteristically slightly above 500?. Impedance match is not necessary, but loading the signal source should be avoided. When the source is 50 or 75?, a DC-blocking capacitor is usually all that is needed. Input amplification is low enough to assure reasonable response time in the case of large signals, but high enough for good AM rejection. After amplification, the input signal drives one port of a multiplier-cell phase detector. The other port is driven by the current-controlled oscillator (ICO). The output of the phase comparator is a voltage proportional to the phase difference of the input and ICO signals. The error signal is filtered with a low-pass filter to provide a DC-correction voltage, and this voltage is converted to a current which is applied to the ICO, shifting the frequency in the direction which causes the input and ICO to have a 90° phase relationship. | |
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